ScalaHDL: a first version is released in github

ScalaHDL: a Scala DSL which enables you to write code for FPGA in Scala, and later converted it into Verilog. You can also simulate and test your FPGA designs in ScalaHDL without converting them into Verilog. By Li Yao(李垚)

Introduction : ScalaHDL

Github: https://github.com/lastland/ScalaHDL

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